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| Title: | 以微影製程製備鉍-銻-碲熱電晶片於能獲與溫度感測之應用
Fabrication of Bi-Sb-Te thermoelectric chips by lithography for energy harvesting and temperature detecting |
| Authors: | 張家豪
Chang, Chia-Hao |
| Contributors: | 陳洋元
Chen, Yang-Yuan
張家豪
Chang, Chia-Hao |
| Keywords: | 熱電晶片
熱電材料
濺鍍
微影製程
Thermoelectric chips
Thermoelectric materials
Sputtering
Lithography |
| Date: | 2022 |
| Issue Date: | 2022-09-02 15:06:38 (UTC+8) |
| Abstract: | 許多看不見的熱能存在於生活當中，如人體發出的溫度；而現今透過熱電晶片，我們能捕獲生活中未善加利用的熱能，且因其尺寸較小且輕薄，僅需要透過體溫與自然之間的溫差，就能輕易捕獲廢熱。如此獲取熱能的技術甚至能使3C穿戴式裝置能在續航與充電上有所突破。
製備熱電晶片第一步透過濺鍍(Sputtering)沉積直徑為1 mm，高為9 μm的P型Bi0.5Sb1.5Te3和N型CuI0.02Bi2Te2.7Se0.3的圓柱，材料沉積在鉻、金下電極上(下電極由電子束蒸鍍機沉積)，而第二步則是懸塗負光阻SU-8作為支撐層，利用半導體製程中的微影(Lithography)，定義出0.8 mm大小的孔洞在P型和N型柱上，經過蝕刻處理後，透過顆粒紙拋光殘留在P型和N型孔洞旁多餘的光阻，確保晶片為平面後，便再蒸鍍鉻、金作為上電極，作為串連導線，便完成熱電晶片的製作。
本篇透過共濺鍍選擇不同元素比例，以此獲得室溫下較佳熱電性質的N型半導體材料。以Bi2Te3組合為基礎，透過參雜較高比例的碲Te元素，室溫下共濺鍍出的Bi1.6Te3.4的席貝克係數(Seebeck) 為-122.8 μV/K。
本篇製備的熱電晶片在4吋矽晶圓上，可分割出四個區塊、單一區塊面積為9平方公分，且每個區塊內含有128對圓柱狀的P型和N型半導體材料、兩者高度皆為9 μm高。該熱電晶片利用紅外光在晶片上方加熱建立出~5°C的溫差下，可得到10 mV的開路電壓，席貝克係數為2.0 mV/K。利用加熱板加熱晶片下方，建立6.8 °C溫差，在120 Ω負載時最大電壓為0.51 mV，功率為2.08×10-9 W。
未來如提升熱電材料性質以及採用更多對數的π-type，使晶片有更大的電壓輸出，就能拓展熱電晶片在生活中的應用，使生活中的廢熱能透過熱電晶片和熱電元件轉換為乾淨能源被人們所用。
Many invisible heat sources exist in our lives, such as the temperature emitted by the human body. Nowadays, through thermoelectric chips, we can capture unused heat in our lives, and because of their small size and thinness, they can easily capture waste heat through the temperature difference between body temperature and nature. This technology of capturing heat energy can even enable 3C wearable devices to make a breakthrough in battery life and charging.
In the first step of preparing thermoelectric chips, P-type Bi0.5Sb1.5Te3 and N-type CuI0.02Bi2Te2.7Se0.3 cylinders with a diameter of 1 mm and a height of 9 μm are deposited by sputtering on chromium and gold lower electrodes (the lower electrodes are deposited by an electron beam vaporizer). In the second step, negative photoresist SU-8 is applied as a support layer, and 0.8 mm sized holes are defined on the P- and N-pillars by using lithography in the semiconductor process. After the etching process, the residual photoresist is polished by particle paper to ensure the wafer is flat, and then chromium and gold are vaporized as the upper electrode and used as a series wire to complete the thermoelectric chips fabrication.
In this paper, we select different element ratios by co-sputtering to obtain N-type semiconductor materials with better thermoelectric properties at room temperature. Based on the Bi2Te3 combination, the Seebeck coefficient of Bi1.6Te3.4 is -122.8 μV/K at room temperature by adding a higher proportion of tellurium Te elements.
The thermoelectric chips prepared in this paper can be divided into four blocks on a 4-inch silicon wafer, each containing 128 pairs of cylindrical P-type and N-type semiconductor materials, with a single block area of 9 square centimeters and a height of 9 μm for P-type and N-type materials. The thermoelectric chip is heated by infrared light above the chip to establish a temperature difference of ~5°C, resulting in an open-circuit voltage of 10 mV with a Seebeck factor of 2.0 mV/K. The maximum voltage is 0.51 mV and power is 2.08 × 10-9 W at a 120 Ω load at a temperature difference of 6.8°C using a hot plate to heat the underside of the wafer.
In the future, if the nature of the thermoelectric materials is improved and more logarithmic π-type is used to make the chip have a larger voltage output, the application of thermoelectric chips in life can be expanded, so that the waste heat in life can be converted into clean energy through the thermoelectric chips and thermoelectric elements. |
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| Description: | 碩士
國立政治大學
應用物理研究所
109755003 |
| Source URI: | http://thesis.lib.nccu.edu.tw/record/#G0109755003 |
| Data Type: | thesis |
| DOI: | 10.6814/NCCU202201453 |
| Appears in Collections: | [應用物理研究所 ] 學位論文
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