A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor

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題名:	A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor
作者:	Kuo;Geng-Sheng;Khan, A.;Watson, P.;Le, D.;Nguyen, T.;Yang, S.;Bennett, P.;Huang, Pokai;Gill, J.;Hawkins, C.;Goodenough, J.;Wang, Demin;Ahmed, I.;Tran, P.;Mak, H.;Kim, Oanh;Martin, F.;Fan, Y.;Ge, D.;Kung, J.;Shek, V. 郭更生
貢獻者:	企管系
日期:	2006-08
上傳時間:	2015-03-06 11:09:14 (UTC+8)
摘要:	An electrical and physical design power optimization methodology and design techniques developed to create an IC with an ARM 1136JF-S microprocessor in 90-nm standard CMOS are presented. Design technology and methodology enhancements to enable multiple supply voltage operation, leakage current and clock rate optimization, single-pass RTL synthesis, VDD selection, power optimization and timing and electrical closure in a multi-VDD domain design are described. A 40% reduction in dynamic and a 46% reduction in leakage power dissipation has been achieved while maintaining a 355-MHz operating clock rate under typical conditions. Functional and electrical design requirements were achieved with the first silicon.
關聯:	IEEE Journal of Solid-state Circuits, 41(8), 1707-1717
資料類型:	article
DOI:	http://dx.doi.org/10.1109/JSSC.2006.877248
顯示於類別:	[企業管理學系] 期刊論文

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